Cell-height scaling is critical for designing advanced semiconductor devices beyond the 14 nm technology node, e.g., at the 7 nm technology node. A known approach for achieving the required cell-height scaling involves the trench silicide (TS) of a logic or memory cell extending past the fins, as depicted in FIGS. 1A and 1B. FIG. 1A schematically illustrates a cross-sectional view along the cut line 1A-1A′ of FIG. 1B, and FIG. 1A is a top view. Adverting to FIGS. 1A and 1B, the known device includes gates 101 across and perpendicular to fins 103 and a shallow trench isolation (STI) layer 105 on the substrate 107. Pairs of raised source/drain (RSD) 109 are on the fins 103 between the gates 101, and a liner 111 is on the downward facing surfaces of the RSD 109 and on the STI layer 107 between the RSD 109. TS 113 are on the RSD 109 and extend past the outside edges of the fins 103, as depicted by the lines 115. Further, an interlayer dielectric (ILD) 117 is between and adjacent to the TS 113. Consequently, there is robust contact between the TS 113 and the RSD 109, but the cell height is relatively large, resulting in a resistance penalty.
A need therefore exists for methodology enabling cell-height scaling beyond the 14 nm technology node without contact area loss or a resistance penalty and the resulting device.